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Preliminary
RF2968
BLUETOOTHTM TRANSCEIVER
11
Typical Applications
* Bluetooth GSM/GPRS/EDGE Cellular Phones * Bluetooth Wireless LAN
* Cordless Phones * Battery-Powered Portable Devices
Product Description
The RF2968 is a monolithic integrated circuit intended for use as a low-cost FSK transceiver in Bluetooth applications. The device is provided in 32-lead plastic LPCC packaging and is designed to provide a fully-functional FSK transceiver. The chip is intended for Bluetooth applications in the 2.4GHz to 2.5GHz ISM band. The IF and demodulation sections of the chip require no external filters or discriminators. The chip also features an image reject front end and a fully programmable synthesizer with integrated oscillator circuitry. Self-calibrating RX and TX IF circuitry optimizes link performance and eliminates manufacturing variations.
BLUETOOTH is a trademark owned by the Bluetooth SIG, Inc., and licensed to RF Micro Devices, Inc.
5.00 0.10 4.75 0.10
-A-B0.40 0.10 0.20
4.75 0.10
5.00 0.10
1.0 MAX 0.50
11 1 (4X)
See Detail A 0.70 0.08 -CSeating Plane
Detail A 0.70 0.08 1.00 MAX 5 m - 20 m -C-
NOTES: 1. Shaded lead indicates Pin 1. 2. Package surface roughness at 1.5 m 0.30.
Optimum Technology Matching(R) Applied
Package Style: LCC, 32-Pin, 5x5
uSi Bi-CMOS
IFDGND VCC7 32 VCC1 1 31
Si BJT
GaAs HBT SiGe HBT
GaAs MESFET Si CMOS
Features
* Fully Monolithic Integrated Transceiver * Self-Calibrating Transceiver
24 PLLGND
11
TRANSCEIVERS
RESNTR+
RESNTR-
RSHUNT
VREG
30
Voltage Regulator
29
28
27
26
25
VCC6
DO
VCO Transmitter VCC2 2 Filter BT = 0.5
TX DATA SYNC 4 MHz ICO LOOP FILTER LO x2 Prescaler 16/17 Synthesizer
Phase Detector/ Charge Pump
* Image Reject Receiver * Bluetooth and BlueRF compatible * Supports Reference Clocks to 40MHz * Smallest Footprint Bluetooth Transceiver
500 kHz
BDATA1 10 MHz BPKTCTL BXTLEN
Chip Control
Address 7
23 BnPWR
TXOUT 3
APPF LO
/4
TX DATA
/4
Phase Detector / Charge Pump
DBus
Address 30 Address 31
16-Bit Shift Register (Read Only)
22 BDCLK
1 MHz 5
Address 3 25 25-Bit Shift Register (Write Only)
21 BDDATA
Receiver LPF/ Equalizer FSK Demodulator
RX DATA
RXIN 4
25-Bit Latch 16 16 16 Address 4 Address 5 Address 6 25
20 BnDEN
1 MHz IF
VCC3 5
APPF LO
60 MHz
Clock / Data Recovery
500 kHz 1 MHz
/2
Div R 19 OSC I
VCC4 6
RX DATA
TX DATA
60 MHz 10 MHz 12 MHz
/60 /6 /5
Ref. Osc.
18 OSC O 17 BRCLK
LPO 7
Phase Detector/ Charge Pump
Div R
Ordering Information
DVDDH 8 9 IREF 10 VCC5 11 D1 12 BPKTCTL 13 BDATA1 14 RECCLK 15 RECDATA 16 BXTLEN
TBD
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
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RF2968
Absolute Maximum Ratings Parameter
Supply Voltage Control Voltages Input RF Level Operating Ambient Temperature Storage Temperature
Preliminary
Ratings
-0.5 to +3.6 -0.5 to VCC +10 -40 to +85 -55 to +125
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall
RF Frequency Range
Specification Min. Typ. Max.
2400 to 2500 1100 to 1350 -50 79 1 -90 -110 -124 13 26 130 85 1 0 28 4 4 50 160 50
Unit
MHz MHz kHz MHz dBc/Hz dBc/Hz dBc/Hz MHz MHz s MHz/V Mbps dBm dB dB s kHz kHz % ns dBc dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
Condition
T=25 C, VCC =3.0V
VCO and PLL Section
VCO Frequency Range Frequency Tolerance RF Channels Step Size SSB Phase Noise 20ppm crystal; -40C to +85C Freq=2.4GHz Freq=2.4GHz, 500kHz Offset Freq=2.4GHz, 2MHz Offset Freq=2.4GHz, 3MHz Offset 10, 11, 12, 13, 20MHz Div2ENB=0; 20, 22, 24, 26, 40MHz. Dual BW =75kHz and 25kHz; BW switch delay=100s VCO Freq=1.2GHz
Reference Frequency Hop Time KVCO
10 20
20 40 175
Transmit Section
Data Rate Output Power Power Control Range Power Control Step Size Gain Step Switching Time Output Impedance Deviation Transmit ISI Min Freq Dev, % EYE Open Zero Crossing Error In-Band Spurious Adjacent Channel Power Second Channel Power >Third Channel Power Out-of-Band Spurious Operation 4
11
TRANSCEIVERS
25 140 115 80 -125
100 175
100 125 -20 -20 -40 -36 -30 -47 -47 -57 -47 -47 -47
From -28dB to 0dB VSWR<2:1 Peak, Data Sequence 00001111 Peak, Data Sequence 01010101 Data Sequence 1010 Reference Data Sequence 00001111 +1/8 Symbol Measurement BW =100kHz
Idle
Measurement BW =100kHz 30MHz to 1GHz 1GHz to 12.75GHz 1.8GHz to 1.9GHz 5.15GHz to 5.3GHz 30MHz to 1 GHz 1GHz to 12.75 GHz 1.8GHz to 1.9GHz 5.15GHz to 5.3GHz
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Preliminary
Parameter
Overall Receive Section
Cascaded Voltage Gain Cascaded Noise Figure Cascaded Input IP3 RX Sensitivity Image Rejection RX Input Impedance Interference Performance Co-Channel Interference, C/ICO-Channel Adjacent (1MHz) Interference, C/I1MHz Adjacent (2MHz) Interference, C/I2MHz Adjacent (>3MHz) Interference, C/I>3MHz Image Frequency Interference, C/Iimage Adjacent (1MHz) Interference to In-Band Image, C/Iimage+1MHz Out-of-Band Blocking Interfering Signal Frequency 30MHz to 2000MHz 2000MHz to 2400MHz 2500MHz to 3000MHz 3000MHz to 12.75GHz Intermodulation Characteristic f1, f2 25 18 8 -14 -85 30 50 100 14 +4 -30 -40 -9 -20 64 dB dB dBm dBm dB dB dB dB dB dB dB
RF2968
Specification Min. Typ. Max. Unit Condition
IF BW=1MHz, BER=10-3 2:1 VSWR max. BER <10-3 (C=Desired Signal/I=Interferer) C=-60dBm C=-60dBm C=-60dBm C=-67dBm C=-67dBm C=-67dBm
BER <10-3, C=-67dBm, tested per evaluation board schematic -10 -27 -27 -10 -39 dBm dBm dBm dBm dBm BER <10-3 (BT=Bluetooth Modulated Signal) f0=-64dBm BT signal f1=sine f2=BT signal |f2-f1|=3MHz, 4MHz or 5MHz f0=2f1-f2 BER <10-3 Measurement BW=100kHz
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TRANSCEIVERS
Maximum Usable Level Spurious Emissions 30MHz to 1GHz 1GHz to 12.75GHz RSSI Operating Range RSSI Resolution RSSI Absolute Accuracy
-20 -57 -47 -20 1 -4 25.5 27.5 20 6 -14 1 -9.5 25 37 4 29.5 8.5
dBm dBm dBm dBm dB dB dB dB dB dBm MHz dB dB
-80
Power level at RX IN pin -60dBm input power
Front End
Voltage Gain Power Gain Noise Figure IIP3
IF Section
IF Frequency Voltage Gain Noise Figure Followed by 1 bit A/D
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RF2968
Parameter
Data Voltages
Logic Low Logic High 0.3 VCC -0.3 2.5 3.3 49 49 1 250 750 3.6 V V V mA mA A A A
Preliminary
Specification Min. Typ. Max. Unit
ZLOAD >10k
Condition
Power Supply
Voltage TX Current Consumption RX Current Consumption Sleep Modes Transmit mode, +4dBm output power Receive mode Sleep mode, no low power clock Sleep mode, low power clock, 12MHz reference Sleep mode, low power clock, other reference
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TRANSCEIVERS
11-120
Rev A13 010912
Preliminary
Pin 1 2 3 Function VCC1 VCC2 TX OUT Description
Supply voltage for the VCO doubler and LO amplifier circuits. Supply voltage for the RX mixers, TX PA, and LNA bias circuits. Transmitter output. TX OUT output impedance is 50 (nominal) when the transmitter is enabled. TX OUT is a high impedance when the transmitter is disabled. Because this pin is DC-biased, an external coupling capacitor is required.
RF2968
Interface Schematic
VCC
10 TX OUT
4
RX IN
Receiver input. RX IN input impedance is a low impedance when the receiver is enabled. RX IN is a high impedance when the receiver is disabled. An internal series inductor is used to tune the input impedance. Supply voltage for the RX input stage (LNA).
RX IN
5
VCC3
VCC3
VCC3
6 7 8 9 10 11 12
VCC4 LPO DVDDH IREF VCC5 D1 BPKTCTL
Supply voltage for the TX mixers and bias circuits of the LO amplifier, LNA, and RX mixers. Low frequency clock output for low power mode. In sleep mode, this pin may provide either a 3.2kHz or 32kHz clock having a 50% duty cycle to the baseband. In other modes, the output is disabled. Supply voltage for the RX IF VGA circuit. Connects an external precision resistor (1% tolerance) for generation of a constant current reference. Supply voltage for the analog IF circuits. This is the output of the charge pump for clock recovery circuit. A RC See pin 26. network from this pin to ground is used to establish the PLL bandwidth. In transmit mode, this pin is used as a strobe to enable the PA stage. In See pin 23. receive mode, the baseband has the option to use this pin to signal the detection of the sync word. The baseband drives this pin high at the end of the sync word, at which time a second DC estimation is performed by sampling the trailer bits. If baseband control is not desired to signal the second DC estimation, then an internal timer is used to mark the end of the sync word. The BBC bit is used to select the baseband control option; the default setting uses the internal timer. Input data to transmitter/output data from receiver. The input data is RXDATA unfiltered data at 1MHz data rate. The pin is bidirectional, switching between data in and data out modes during Transmit and Receive TX DATA modes respectively. Recovered clock output. See pin 17. Recovered data output. This pin is part of the chip power control circuit. It is used to enable/disable "sleep" mode of chip.
BXTLEN
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TRANSCEIVERS
13
BDATA1
BDATA1
14 15 16
RECCLK RECDATA BXTLEN
See pin 17.
VCC
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RF2968
Pin 17 Function BRCLK Description
Reference clock output. This is a crystal controlled reference clock in the 10-40MHz range, typically 13MHz.
Preliminary
Interface Schematic
VCC
BRCLK
18 19
OSC O OSC I
Same as pin 19. The OSC pins are used to produce the reference frequency by means of negative feedback. A crystal and resistor are placed in parallel from OSC I to OSC O to provide the feedback path and establish the resonant frequency. A shunt capacitor is placed on each OSC pin to provide the proper loading of the crystal. If an external reference is used, it is connected to OSC I through a DC-blocking capacitor, and OSC O is connected to OSC I through a 470k resistor. Latches data entered into the serial port. Data is clocked into the latch on the rising edge of BnDEN. Serial data port. Read/write data is sent through this pin into / out of the on chip shift register. Read data is transferred on the rising edge of BDCLK. Write data is transferred on the falling edge of BDCLK. Serial port input clock.This pin is used to clock data into the serial port. To minimize the hop frequency programming time, a BDCLK frequency of 10-20MHz is recommended. This pin is part of the chip power control circuit. It is used to power up the chip from the "off" state.
See pin 19.
OSC I
OSC O
20 21 22 23
BnDEN BDDATA BDCLK BnPWR
See pin 23.
READ DATA Pin 21 WRITE DATA
See pin 23.
VCC
BnPWR
24
PLL GND VCC6 D0
11
TRANSCEIVERS
25 26
Ground connection for the RF synthesizer, crystal oscillator, and serial port. Supply voltage for the RF synthesizer, crystal oscillator, and serial port. This is the output of the charge pump for the RF PLL. An RC network from this pin to ground is used to establish the PLL bandwidth. To minimize synthesizer settling time and phase noise, a dual loop bandwidth scheme is implemented. During the initial period of frequency acquisition, a wide loop bandwidth is used. RSHUNT is used to switch to a narrow loop bandwidth near the end of the frequency acquisition, providing improved VCO phase noise. The time at which the bandwidth switches is set by the PLLDel bits. Switches the loop filter from wide to narrow bandwidth by shunting the midpoint of two external series resistors to ground. The RESNTR pins are used to supply DC voltage to the VCO as well as to tune the center frequency of the VCO. Two inductors are required between RESNTR- and RESNTR+ to resonate with the internal capacitance. Inductance of traces from the RESNTR pins to the inductor should be taken into account in the board layout.
VCC
D0
27 28
RSHUNT RESNTR-
RESNTR+ D0 4 k
RESNTR-
11-122
Rev A13 010912
Preliminary
Pin 29 30 Function RESNTR+ VREG Description
See pin 28. Voltage Regulator Output (2.2V). A bypass capacitor from this pin to ground is required. This voltage is used to bias the VCO through the tank circuit tied to pins 28 and 29.
RF2968
Interface Schematic
VCC
VREG
31 32
IFDGND VCC7 ESD
Ground connection for the digital IF circuits. Supply voltage for the digital IF circuits. This diode structure is used to provide electrostatic discharge protection to 3kV using the Human body model. The following pins are protected: 6-7, 9-17, 20-27, 30-32.
VCC
Die Flag
GND
Ground connection for all circuits other than those grounded through dedicated pins. The die flag must be connected to the ground plane with very low inductance for best performance.
11
TRANSCEIVERS
Rev A13 010912
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RF2968
Theory of Operation
Preliminary
The RF2968 is the first in a family of 2.4GHz transceivers developed specifically for Bluetooth applications. It operates as a Power Class 2 (+4dBm) or Class 3 (0dBm) Bluetooth device and is fully compliant to Version 1.0b of the Bluetooth Radio Specification. For Power Class 1 (+20dBm) applications, the RF2968 may be used with a power amplifier such as the RF2172. Processed in 0.35um silicon Bi-CMOS and packaged in a 5mm-square, industry-standard 32-pin leadless plastic package, the RF2968 provides high performance at a very low cost. With integrated IF filtering, the RF2968 requires minimal external components and eliminates the need for costly components such as IF SAW filters and baluns. The high impedance 'off' states of the receiver input and transmitter output also eliminate the need for an external transmit/receive (T/R) switch. A complete Bluetooth solution may be implemented with the RF2968 in conjunction with an antenna, RF bandpass filter, and baseband controller. In addition to the RF signal processing, the RF2968 also performs the baseband functions of data demodulation, DC compensation, and data and clock recovery while access code correlation takes place in the baseband device. The RF2968 transmitter output is internally matched to 50, and requires an AC-coupling capacitor. The receiver's low noise amplifier (LNA) input (RXIN pin) is internally matched to present a 50 impedance to the front end filter. A single front end filter may be shared by the transmitter and receiver by simply connecting the TXOUT coupling capacitor to RXIN. Alternatively, the transmit path may be externally amplified to +20dBm, which, in conjunction with the RF2968's transmit gain control and received signal strength indicator (RSSI), allows Bluetooth-compliant operation for Power Class 1. The RSSI data is accessed via the serial port and provides a 1dB resolution over the RX input power range of -20to80dBm. Transmit gain control is adjustable in 4dB steps and is also set via the serial port. Baseband data is sent to the transmitter via the BDATA1 pin, which is a bidirectional pin, acting as an input in transmit mode and an output in receive mode. The RF2968 performs the Gaussian filtering of the baseband data, FSK-modulates the IF current controlled oscillator (ICO), and upconverts the IF to the RF channel frequency. The on-chip voltage controlled oscillator (VCO) is frequency synthesized to one half of the required local oscillator (LO) frequency and then doubled to produce the correct LO frequency. Two external tank inductors between RESNTR+ and RESNTR- set the tuning range of the VCO. Voltage is supplied to the VCO from an on-chip regulator that is connected to the midpoint of the two tank inductors through a filtering network. Due to the fast frequency hopping requirements of Bluetooth, the loop filter components (connected to pins D0 and RSHUNT) are especially critical as they largely determine the hopping and settling time of the VCO. Use of the component values as given in the Application Schematic is strongly recommended. The RF2968 may use either a 10MHz, 11MHz, 12MHz, 13MHz, or 20MHz reference clock frequency and can also support a reference clock at double these frequencies to provide a migration path toward smaller end-product designs. This clock may be supplied by an external reference applied directly to OSC I through a DC-blocking capacitor. If an external reference is not available, then a crystal and two capacitors may be used to complete the reference oscillator circuitry contained on-chip. For either an externally or internally generated referenced frequency, a resistor between OSC I and OSC O is required for proper biasing. The frequency tolerance of the reference clock must be 20ppm or better to assure that the maximum allowed system frequency error remains within the demodulation bandwidth of the RF2968. A selectable 3.2kHz or 32kHz low power mode clock is available at the LPO pin to supply the baseband device with a low frequency clock in sleep mode. Where minimal sleep mode power consumption is a concern and reference clock frequency selection is flexible, a 12MHz reference clock should be chosen. The receiver uses a low-IF architecture to minimize external component count. The RF signal is downconverted to 1MHz, allowing IF filtering to be incorporated on chip. Demodulated data is output at the BDATA1 pin. Further data processing is performed by the data and clock recovery circuitry, which utilizes a baseband PLL. Pin D1 is the loop filter connection for the baseband PLL. The synchronized data and clock are output at pins RECDATA and RECCLK. If the baseband device used with the RF2968 performs the clock recovery, then the D1 loop filter components may be omitted. The interface between the RF2968 and baseband device is described in the 'Application Information' section of the fulllength datasheet available from the RFMD web site (www.rfmd.com).
11
TRANSCEIVERS
11-124
Rev A13 010912
Preliminary
Detailed Functional Block Diagram
RESNTR+ RESNTRRSHUNT IFDGND VREG VCC7 32 VCC1 1 31 30 29 28 27 26 25 VCC6 DO
RF2968
VCO Transmitter VCC2 2 Filter BT = 0.5
TX DATA SYNC 4 MHz ICO LOOP FILTER LO x2 Prescaler 16/17 Synthesizer
24 PLLGND
Phase Detector/ Charge Pump
500 kHz
Address 7
BDATA1 10 MHz BPKTCTL BXTLEN
Chip Control
23 BnPWR
TXOUT 3
APPF LO
/4
TX DATA
/4
Phase Detector / Charge Pump
DBus
Address 30 Address 31
16-Bit Shift Register (Read Only)
22 BDCLK
1 MHz 5
Address 3 25 25-Bit Shift Register (Write Only)
21 BDDATA
Receiver LPF/ Equalizer FSK Demodulator
RX DATA
RXIN 4
25-Bit Latch 16 16 16 Address 4 Address 5 Address 6 25
20 BnDEN
1 MHz IF
VCC3 5
APPF LO
60 MHz
Clock / Data Recovery
500 kHz 1 MHz
/2
Div R 19 OSC I
VCC4 6
RX DATA
TX DATA
60 MHz 10 MHz 12 MHz
/60 /6 /5
Phase Detector/ Charge Pump
Ref. Osc.
18 OSC O 17 BRCLK
LPO 7
Div R
DVDDH 8 9 IREF 10 VCC5 11 D1 12 BPKTCTL 13 BDATA1 14 RECCLK 15 RECDATA 16 BXTLEN
Pin Out
RESNTR+ RESNTRRSHUNT IFDGND VREG VCC7 VCC6 DO
11
24 23 22 21 20 19 18 17 PLL GND BnPWR BDCLK BDDATA BnDEN OSC I OSC O BRCLK
32 VCC1 VCC2 TX OUT RX IN VCC3 VCC4 LPO DVDDH 1 2 3 4 5 6 7 8 9 IREF
31
30
29
28
27
26
25
10 VCC5
11 D1
12 BPKTCTL
13 BDATA1
14 RECCLK
15 RECDATA
16 BXTLEN
Rev A13 010912
11-125
TRANSCEIVERS
RF2968
Application Schematic for Typical GSM Handset
(Assumes Clock Recovery Performed by Baseband)
Preliminary
820 1 F 1 F
43 k
20 k
330 pF
30 pF
VCC
3.9 nH
3.9 nH
VCC
22 nF* 32 1 2 FL1 22 nF 3 4 5 VCC 22 nF* 6 19 18 17 9 10 11 12 13 14 15 16 22 21 20 31 30 29 28 27 26 25 24 23
22 nF*
BnPWR BDCLK BDDATA BnDEN REF IN 470 k 1 nF
11
TRANSCEIVERS
LPO
7 8
BRCLK BXTLEN BDATA1
20 k 1%
BPKTCTL
VCC *Note: Required supply filtering may vary depending on implementation. 22 nF*
11-126
Rev A13 010912
Preliminary
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
RF2968
P1 BDCLK BDDATA BnDEN BRCLK VCC R6 820 C13 1 F C12 1 F R5 43 k R4 20 k C11 330 pF L2 3.9 nH VCC C1* 22 nF 32 1 C2 22 nF 2 3 RX IN/TX OUT 4 5 C3* 22 nF VCC LPO 6 7 8 9 10 11 12 13 14 15 16 21 20 19 18 17 BDDATA BnDEN 31 30 29 28 27 26 25 24 23 22 BnPWR BDCLK C9* 22 nF L1 3.9 nH VCC C10 30 pF BXTLEN RECDATA RECCLK BPKTCTL 10 9 8 7 6 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 LPO VCC BnPWR BDATA1
CON20
FL1
11
TRANSCEIVERS
R3 470 k
Y1 13 MHz
C8 47 pF C7 47 pF BRCLK BXTLEN RECDATA
R1 20 k 1%
RECCLK BDATA1 BPKTCTL
VCC C4* 22 nF C5 100 pF
*Note: Required supply filtering may vary depending on implementation.
C6 2.7 nF R2 22 k
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RF2968
Application Information
Preliminary
Baseband Interface The RF2968 RF transceiver serves as the physical layer (PHY) in a Bluetooth system and supports the BlueRF interface between PHY and baseband devices. The RF2968 contains the data demodulation, DC compensation, and data and clock extraction circuitry while the access code correlator function takes place in the baseband. There are two interfaces between the RF2968 and the baseband. The serial interface provides the path for control data exchange, and the bidirectional interface provides the path for modem, timing, and chip power control signals. Figure 1 shows bidirectional signals with arrowheads on both ends of the line.
BDATA1
Bidirectional Interface
BASEBAND
BXTLEN BRCLK BnPWR BDDATA
Bidirectional Interface
BPKTCTL
SPI Master
BDCLK BnDEN
Figure1. Baseband/RF2968 Interface Serial Interface Control data is exchanged between the RF2968 and the baseband by means of the DBus serial interface protocol. BDCLK, BDDATA, and BnDEN are the signals comprising the serial interface. The baseband is the master device, initiating all accesses to the RF2968 registers. The data registers of the RF2968 are programmed or recalled according to the specified command format and address assignments. Data packets are transmitted MSB first. Serial Data Packet Format
Field Device Address Read/Write Register Address Data Number of Bits 3 [A7:A5] 1 [R/W] 5 [A4:A0] 16 [D15:D0] Comments "101" for PHY "1"=Read, "0"=Write Maximum of 32 registers The RF2968 is programmed in Write mode and returns its register contents in Read mode.
11
TRANSCEIVERS
During a write, the baseband drives out each bit of the packet on the falling edge of BDCLK. The RF2968's data register is updated with the shift register contents on the first falling edge of BDCLK after BnDEN is driven high. See Figure 2.
BDCLK BDDATA BnDEN
A7 A6 A5 A4 A3 A2 A1 A0 D15 D14
... ...
SPI Slave
D2
D1
D0
don't care
RF2968
A7 A6
R/W= write = 0
Figure 2. DBus Write Programming Diagram
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Rev A13 010912
Preliminary
RF2968
In a read operation, the baseband sends the device address, READ bit (R/W = 1), and register address to the RF2968 followed by a "turn-around" bit which lasts half a clock cycle. This turn-around allows the RF2968 to drive its requested data, via BDDATA, on the rising edges of BDCLK. Following the transfer of the last data bit (D[0]), the baseband drives BnDEN high and resumes control of BDDATA on the falling edge of the first BDCLK pulse after BnDEN is driven high. See Figure 3.
Floating Master Driving BDDATA BDCLK BDDATA
A7 A6 A5 A4 A3 A2 A1 A0 D15 D14
Floating Slave Driving BDDATA
... ...
D2
D1
D0
don't care
A7
A6
R/W = read = 1 BnDEN
turn-around
turn-around
Figure 3. DBus Read Programming Diagram
Register Definition The register address field allows up to 32 registers for various functions. The RF2968 implements only register addresses 3-7 and 30-31. Register 3 - IF Register 1 (Read-Only)
Bit Number 7 - 15 0 -6 Bit Name N/A RSSI[6:0] Not Assigned The RSSI value indicates the average power measured during the first 10s after a packet has been detected. The baseband reads this register to obtain the current received signal strength indicator measurement. The RSSI value may range from 0dBm to -127dBm in 1dB increments. (All 0's indicates 0dBm; all 1's indicates -127dBm.) The RSSI circuitry is designed to operate from -20dBm to -80dBm with an accuracy of 4dB at -60dBm. Example: RSSI[6:0]=[110101] indicates -53dBm. Comments
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TRANSCEIVERS
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RF2968
Register 4 - IF Register 2 (Write-Only)
Bit Number 12-15 11 Bit Name N/A ChopENB Not Assigned Comments
Preliminary
Enables circuitry that significantly reduces the levels of RF PLL comparison frequency spurious responses. 1: Spur cancellation disabled. 0: Normal mode. Spur cancellation enabled. Enables an additional divide-by-two operation in the reference divider circuitry to accommodate the use of a 20MHz-40MHz crystal or clock. This allows a migration path to higher reference frequencies. 1: Normal mode. 10, 11, 12, 13, or 20MHz reference clock. 0: Expanded mode. Reference clock is double that allowed in normal mode. Determines the function of the low power mode clock (output at pin 7) when the device is in Sleep mode according to the table below. In non-Sleep modes, the output is disabled. Sets the gain of the transmitter path. The gain is normally programmed immediately after the register write to enter the WAIT DATA SYNC state in Power Class 1 applications. Gain is adjustable from 0dBto-28dB in 4dB steps. [All 0's indicates high gain (0dB attenuation); all 1's indicates low gain (28dB attenuation).] Example: Gain[2:0]=[011] indicates 12dB attenuation. 1: Slow AGC disabled. 0: Normal mode. Slow AGC enabled. Not Assigned Selects a path in the RX data DC estimation circuit. 1: Selects the DC estimation path that is AC coupled and which is normally used for the payload part of packet. 0: Selects the fast DC estimation RX data path normally used for the access code of packet. Sets the receiver gain according to the table below.
10
Div2ENB
8-9
LPO[1:0]
5-7
Gain[2:0]
4 3 2
ENSlowAGCB N/A TPL_AC
0-1
TDet[1:0]
LPO [1:0]:
11
TRANSCEIVERS
LPO[1:0] 0X 10 11
Output at LPO (Pin 7) 32kHz clock 3.2kHz clock Clock disabled
TDet [1:0]:
TDet[1:0] 11 10 01 00 VGA Gain (dB) -11 4.5 4.5 20 Filter Gain (dB) 1.5 1.5 17 17 Total Gain (dB) -9.5 6.0 21.5 37.0 15.5 15.5 15.5 Step Size (dB)
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Preliminary
Register 5 - IF Register 3 (Write-Only)
Bit Number 15 Bit Name BypassSM Comments
RF2968
Selects or bypasses the state machine. 1: Bypass mode. Internal power-up signals can be directly controlled by programming of the respective bits in this register [0:3, 6:7]. 0: Normal mode. All internally controlled power-up signals are derived from the state machine. Selects baseband control or internal timer control for determining the time at which to perform DC estimation on the trailer bits. 1: Baseband control. The baseband drives BPKTCTL high at the end of the sync word. 0: Internal timer control. Not assigned. IF test mode enable. Used only in IC verification; not for use in end product. 1: IF test mode 0: Normal mode Calibration which compensates for the gain of the LNA, mixer, and VGA. See "Special Modes: Calibration". Calibrates the K0 (gain of the current controlled oscillator) of the TX PLL and, by nature of the design, calibrates the K0 of the RX PLL. See "Special Modes: Calibration". Calibration which compensates for the offset and the amplitude of the Gaussian TX data that modulates the TX PLL ICO. See "Special Modes: Calibration". 1: Loopback mode. The TX IF output is looped back to the RX IF input. 0: Normal mode Powers up the crystal oscillator circuitry. See "BypassSM" bit. 1: Power on 0: Power off Powers up the frequency multiplier for the FM demodulator clock. See "Bypass SM" bit. 1: Power on 0: Power off Calibrates the channel filter, demodulator low pass filter, and AC coupling filter in the DC estimation circuit in the receiver, as well as the Gaussian filter and GFSK harmonic filter in the transmitter. See "Special Modes: Calibration". Calibration which compensates for the offset of the RX data path in the RX PLL interface circuit. See "Special Modes: Calibration". Powers up the transmit output amplifier. See "BypassSM" bit. 1: Power on 0: Power off Powers up all receiver and synthesizer circuits. See "BypassSM" bit. 1: Power on 0: Power off Selects the loop bandwidth of the RF PLL by controlling the state of the RSHUNT pin. Under state machine control, this switch is executed according to the setting of the PLLDel[1:0] bits. 1: Narrow bandwidth. RSHUNT is short-circuited to ground. 0: Wide bandwidth. RSHUNT is a high impedance. Powers up all transmitter and synthesizer circuits except for the output amplifier. See "BypassSM" bit. 1: Power on 0: Power off
14
BBC
13 12
N/A Test
11 10 9 8 7
CalRxVGA Cal_Tx_PLL Cal_Gauss_Cell Loopback PU_XTAL
6
PU_MULT
5
CalRxFil
4 3
CalRXPLL_Int PU_PA
11
TRANSCEIVERS
2
PU_RX
1
PLL_BW
0
PU_TX
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RF2968
Register 6 - IF Register 4 (Write-Only)
Bit Number 0-15 Bit Name N/A Not Assigned Comments
Preliminary
Register 7 - PLL Control (Write-Only)
Bit Number 15 Bit Name Comments Set_Tx_PLL_LF_Ext Configures the LPO pin as a test pin when bits LPO[1:0] are set high. 1: Test mode. LPO is connected to the IF PLL loop filter of the transmitter. (See "Special Modes: Transmitter Test Mode".) 0: Normal mode. LPO is not connected to the IF PLL loop filter of the transmitter. PLLDel [1:0] Determines the time in which the PLL remains in high bandwidth mode before switching to low bandwidth mode. In high bandwidth mode, the PLL loop bandwidth is optimized for fast frequency locking. In low bandwidth mode, the loop bandwidth is optimized for low phase noise. See below. See also pin descriptions of D0 and RSHUNT, and bit PLL_BW (Register 5, Bit 1). Configures the RSSI circuitry to operate continuously for test purposes. 1: Test mode. Continuous operation. 0: Normal mode. Packet-based operation. Selects the external crystal frequency. See below. Powers up the TX voltage and current bias circuits and the TX PLL's ICO voltage threshold set circuit. Powers up the RX voltage and current bias circuits. Sets the RF PLL frequency. See below.
13 - 14
12
RSSI_Test
9 - 11 8 7 0-6
DivR [2:0] TX_EN RX_EN PLL [6:0]
PLLDel [1:0]:
PLLDel [1:0] 00 01 Delay (us) 0 50 100 150
11
TRANSCEIVERS
10 11
DivR [2:0]:
DivR [2:0] 011 100 101 110 111 Crystal Freq (MHz) 12 10 11 13 20
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Preliminary
PLL[6:0]:
RF2968
These bits determine the local oscillator (LO) frequency (i.e., the frequency at the doubler output) for both RX and TX modes. The LO frequency is set 1MHz above the channel center frequency. The PLL [6:0] data bits represent the frequency offset (FOFFSET) in MHz from a base frequency of 2400MHz. For the normal Bluetooth frequency range of 2402MHz to 2480MHz, FOFFSET will range from 3 to 81; for the optional extended Bluetooth range (up to 2497MHz), FOFFSET will range from 3 to 98 (high-side injection assumed in both cases). Example: Assume a channel frequency of 2448MHz. The LO frequency is then: 2448+1=2449MHz, and FOFFSET is: 2449-2400=49. PLL [6:0] is then:0110001 Register 30 - Manufacturer's ID Code LSB's (Read-Only)
Bit Number 0 - 15 Bit Name ID_Code [15:0] Comments Lower 16 bits of manufacturer's code. The fixed "1" LSB of the manufacturer code is read at bit 0.
Register 31 - Manufacturer's ID Code MSB's (Read-Only)
Bit Number 0 - 15 Bit Name ID_Code [31:16] Comments Upper 16 bits of manufacturer's code. The MSB of the version number is read at bit 15. The RF2968 code is hex10B9825D.
Bidirectional Interface Data Exchange and Timing All bidirectional timing may be derived from BRCLK, which is generated by the RF2968. The RF2968 uses the falling edges of BRCLK, and the baseband uses the rising edges. Figure 4 shows the general timing for the case of data being transferred from the RF2968 to the baseband.
BB Data Sampling Points BRCLK
11
TRANSCEIVERS
BDATA1
Figure 4. General Bidirectional Timing (RF2968 writing to baseband)
State Machine Control The chip control circuitry of the RF2968 places the device into the required transmit, receive or power saving mode by controlling the power down and reset states of all other circuits in the device. The chip control inputs come from the baseband device (BnPWR, BXTLEN, BPKTCTL, BDATA1) via the bidirectional interface and from the registers at the output of the DBus block (RXEN, TXEN). State machines in the baseband and the RF2968 maintain the state which controls the direction of the bidirectional lines. The baseband controls the state machine in the RF2968 and ensures that data contentions do not occur during reset and normal operation. The control of individual sections of the RF2968 in each state is as follows.
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RF2968
State OFF PWRON WAIT XTL HOLD XTL IDLE SLEEP Description All circuits are powered down and reset; configuration data is lost. (CLRB=0) Reset is released (CLRB=1) and the oscillator is turned on (PDXTAL=1).
Preliminary
This mode is entered when the oscillator has settled. Configuration data can be read through the DBus interface. This is a standby mode. Data can be read into the control registers (through the DBus) and the oscillator remains on. All other circuits are powered down. The device normally enters this mode from IDLE, in which case every circuit is powered down but not reset, so that configuration data is retained. The device may also enter this mode from any other except PWRON WAIT XTL or HOLD XTL, but the TXEN and RXEN functions are not overridden, so that TX and RX circuits may remain on. The oscillator is turned on (PDXTAL=1) and allowed to settle before returning to IDLE mode. This is the start of the transmit sequence. This mode is entered by the baseband writing to the control registers (through the DBus). When this happens, TXEN goes high, turning on the synthesizer and initializing a fixed delay, after which all the transmit circuits (except for the PA) are turned on (PD_TX=1). The baseband waits 175s before it starts sending transmit data to the RF2968 (to allow the synthesizer to settle). The device cannot be in both transmit and receive modes at the same time, so RXEN must be low to enter this mode. A transition on BDATA1 (0 to 1) starts the synchronization of data between the RF2968 and the baseband device. The PA is powered up (PDPA=1) and ready to begin transmitting. Data is transmitted in this mode. (The synthesizer has settled and the data path synchronized.) The PA is powered down (PDPA=0). 1s later, the synthesizer and the rest of the transmit circuits are powered down (PD_TX=0). This delay prevents any "unwanted transmission" during power down. The device then returns to IDLE mode when the baseband writes to the control registers and drives TXEN low. This is the start of the receive sequence and is entered from IDLE mode when a control register write from the baseband forces RXEN high. This turns on the synthesizer and starts a timer which powers up the receive path circuits after a fixed delay (PD_RX=1). The baseband device expects to receive data 175s after the control register write. Received data is sent to the baseband device via BDATA1 (unsynchronized) and RECDATA (synchronized with RECCLK). Within this state, there are two DC estimation modes. In the "access code" mode, the RF2968 uses a fast DC estimation to adjust for large frequency offsets. An internal timer (or alternatively BPKTCTL) signals the end of the sync word, placing the DC estimation circuitry in the "payload" mode, in which compensation is made for small frequency offsets. A control register write from the baseband drives RXEN low and returns the device to IDLE mode. This turns off the receive path (PD_RX=0) and the synthesizer.
WAIT XTL WAIT DATA SYNC
DATA SYNC ENABLE PA TX DATA DISABLE PA
RX PLL WAIT
RX DATA
11
TRANSCEIVERS
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Preliminary
State Machine
RF2968
The RF2968 state machine is clocked with a 1MHz signal which is derived from the reference oscillator. (The mark space ratio of this 1MHz clock and its precise frequency are not important.) The inputs and outputs for all the states are summarized in the table below. Table 1. State Machine Inputs and Outputs
Inputs Previous State X OFF PWRON WAIT HOLD XTL IDLE SLEEP WAIT XTL IDLE WAIT DATA DATA SYNC ENABLE PA TX DATA DISABLE PA IDLE RX PLL WAIT RX DATA Present State OFF PWRON WAIT HOLD XTL IDLE SLEEP WAIT XTL IDLE WAIT DATA SYNC DATA SYNC ENABLE PA TX DATA DISABLE PA IDLE RX PLL WAIT RX DATA IDLE
a
Outputs
BnPWR BXTLEN BDATA1 BPKTCTL RXEN TXEN PDXTAL CLRB PDTX PDPA PDRX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 X 1 1 X X X
X
X X X X X X X 0e 0e 1 1 0 X X X X
X X 0 0 0 0 0 0 X X X X X
f
X X 0 0 0 0 0 1 1 1 1 1 0 0 0 X
0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1b 1 1 1 0
c
0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1d 1 0
X X X X X X X X X
0 0 0 0
1 1 0
Notes: a. When the inputs try to force the controller into an undefined or illegal state, the state machine will remain in its present state (e.g., if the present state is IDLE and the inputs try to force the device to TX DATA, the chip will stay in IDLE mode). b. PD_TX goes high after a fixed delay following TXEN going high. c. 1s delay from the PD_PA going low to PD_TX going low. d. PD_RX goes high after a fixed delay following RXEN going high. e. BPKTCTL must be low to distinguish DATA SYNC from ENABLE PA. f. If RXEN=1 when entering IDLE from DISABLE PA, then IDLE is held for 1s, after which the state transitions to RX PLL WAIT.
11
TRANSCEIVERS
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RF2968
Special Modes of Operation Calibration
Preliminary
When the RF2968 is Reset (CLRB=0), all calibration values are cleared. Therefore, after the RF2968 is powered up from the OFF state, it must be instructed to perform its self-calibration. Circuits requiring calibration include the RX variable gain amplifier (VGA), TX and RX PLL's, RX channel filter, RX data paths, and TX Gaussian filter. Calibration instructions are sent from the baseband to the RF2968 via the serial port (addressing Registers 5 and 7) and must be performed in the order shown in the table below. After a calibration instruction is sent, the baseband must delay for the length of time indicated before sending the next calibration instruction; this allows time for the RF2968 circuits to settle and execute the instruction. At initialization, BypassSM, PU_XTAL, PU_MULT, and TX_EN are set high and remain so for the duration of the calibration. Register 7 is only addressed during initialization to set TX_EN and configure the reference frequency and RF PLL frequency.
.
Bit Settings for Calibration Sequencea Calibration Steps Initialization of PLL Initialization of Chip Control Calibrate KO of TX and RX IF PLL's Calibrate Gaussian TX and RX VGA Calibrate IF Filters Calibrate RX Offsets Return Chip Control to State Machine Register 15 14 13 12 11 10 7 5 5 5 5 5 5 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x
b
9 x
b
8 1 0 0 0 0 0 0
7 0 1 1 1 1 1 0
6 x
c
5 x
c
4 x
c
3 x
c
2 x
c
1 x
c
0 x
c
Required Time (usec) 0d 2500 1024 285 608 64 0 4481
x
b
0 0 1 0 0 0
0 1 0 0 0 0
0 0 1 0 0 0
1 1 1 1 1 0
0 0 0 1 0 0
0 0 0 0 1 0
0 0 0 0 0 0
0 0 1 1 1 0
0 0 0 0 0 0
0 0 1 1 0 0
Total Calibration Time:
11
Notes:
TRANSCEIVERS
a) Shaded cells indicate no change from previous state. b) Set according to reference frequency. c) Set RF PLL frequency to a valid frequency (LO=2403 to 2481MHz). d) Register 5 may be programmed immediately after Register 7. Transmitter Test Mode: During normal TX mode, the transmitter's IF PLL is opened for modulation of the current controlled oscillator (ICO) for a short period of time (0.4 to 3ms). For development purposes, open-loop modulation may be performed for an indefinite period of time by externally supplying the required ICO control voltage. This allows the ICO to maintain a locked condition. Transmitter Test Mode utilizes the LPO pin, which is switched to the output of the internal loop filter of the transmitter's IF ICO when Set_Tx_PLL_LF_Ext (Register 7, Bit 15) is set high and the 3.2kHz/32kHz low power oscillator is not in use. This pin may be used either to monitor the control voltage during a packet transmission or to externally supply the control voltage for an extended or continuous transmission. When monitoring the ICO control voltage, the voltage on the LPO pin will drift from its initial voltage as the transmission time increases, but should remain in the range of 0.7V to 0.9V. When supplying the ICO control voltage, the voltage to be applied to the LPO pin should be equal to the initial voltage measured when monitoring.
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